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FEATURES 0.2 LSB (0.00031%) Typ Peak DNL and INL 0.5 LSB (0.00076%) Typ Unipolar Offset, Bipolar Zero 17-Bit Monotonicity Guaranteed 18-Bit Resolution (in Serial Mode) Complete 16/18-Bit D/A Function On-Chip Output Amplifier On-Chip Buried Zener Voltage Reference Microprocessor Compatible Serial or Byte Input Double Buffered Latches Asynchronous Clear Function Serial Output Pin Facilitates Daisy Chaining Pin Strappable Unipolar or Bipolar Output Low THD+N: 0.005% MUX Output Control on Power-Up and Supply Glitches PRODUCT DESCRIPTION
UNI/ BIP CLR 17 OR LBE HBE 18 SER 19 CLR 20 LDAC 21 REF IN 25
16/18-Bit Self-Calibrating Serial/Byte DACPORT AD760
FUNCTIONAL BLOCK DIAGRAM
MSB/ 18/16 SIN LSB SERIAL OR OR OR DB0 DB1 DB2
14 13 12
CS
16
DB7
7
AD760
CONTROL LOGIC
16/18-BIT INPUT REGISTER 10k 16/18-BIT DAC LATCH 10k MAIN DAC 9.95k RAM
24 15
SOUT SPAN/ BIP OFF
23 27 28
VOUT MUXOUT MUX I N AGND
REF OUT 26
+10V REF
CALIBRATION DAC
22
CALIBRATION SEQUENCER
1 2 3 4 5 6
The AD760 is a complete 16/18-bit self-calibrating monolithic DAC (DACPORT(R)) with onboard voltage reference, double buffered latches and output amplifier. It is manufactured on Analog Devices' BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry. Self-calibration is initiated by simply pulsing the CAL pin low. The CALOK pin indicates when calibration has been successfully completed. The output multiplexer (MUXOUT) can be used to send the output to the bottom of the output range during calibration. Data can be loaded into the AD760 as straight binary, serial data or as two 8-bit bytes. In serial mode, 16-bit or 18-bit data can be used and the serial mode input format is pin selectable, to be MSB or LSB first. This is made possible by three digital input pins which have dual functions (Pins 12, 13, and 14). In byte mode the user can similarly define whether the high byte or low byte is loaded first. The serial output (SOUT) pin allows the user to daisy chain several AD760s by shifting the data through the input latch into the next DAC thus minimizing the number of control lines required in a multiple DAC application. The double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multi-DAC system. The asynchronous CLR function can be configured to clear the output to minus full-scale or midscale depending on the state of Pin 17 when CLR is strobed. The AD760 also powers up with the
CALOK
CAL
-VEE
+VCC
+VLL
DGND
MUX output in a predetermined state by means of a digital and analog power supply detection circuit. This is particularly useful for robotic and industrial control applications. The AD760 is available in a 28-pin, 600 mil cerdip package. The AQ version is specified from -40C to +85C.
RELATIVE ACCURACY - LSB
0.75
VOUT = -10V TO +10V RL = 2k CL = 1000pF
0.25 0 -0.25
-0.75 0 16384 32768 INPUT CODE - Decimal 49152 65535
Typical Integral Nonlinearity
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
DACPORT is a registered trademark of Analog Devices, Inc. (c) Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD760-SPECIFICATIONS (@ T = +25C, V
A
CC
= +15 V, VEE = -15 V, VLL = + 5 V, unless otherwise noted)
AD760AQ Typ
Model RESOLUTION1 TRANSFER FUNCTION CHARACTERISTICS2 With Calibration @ TCAL3; -40C T CAL +85C Integral Nonlinearity Differential Nonlinearity Monotonicity Unipolar Offset Bipolar Zero Error Without Calibration Integral Nonlinearity TMIN to TMAX Integral Nonlinearity Drift Differential Nonlinearity TMIN to TMAX Differential Nonlinearity Drift Monotonicity Over Temperature Unipolar Offset Unipolar Offset Drift (TMIN to TMAX) Bipolar Zero Error Bipolar Zero Error Drift (TMIN to TMAX) Gain Error4, 5 Gain Drift5 (TMIN to TMAX) DAC Gain Error6 DAC Gain Drift6 (TMIN to TMAX) INPUT RESISTANCE REFIN SPAN/BIP OFF REFERENCE OUTPUT Voltage Drift External Current7 Capacitive Load Short Circuit Current Long-Term Stability OUTPUT CHARACTERISTICS2 Output Voltage Range Unipolar Configuration Bipolar Configuration Output Current Capacitive Load Short Circuit Current MUXOUT Resistance DIGITAL INPUTS (TMIN to TMAX) VIH (Logic "1") VIL (Logic "0") IIH (VIH = VLL) IIL (VIL = 0 V) DIGITAL OUTPUT (TMIN to TMAX) VOH (IOH = -0.6 mA) VOL (IOL = 1.6 mA) POWER SUPPLIES Voltage VCC8 VEE8 VLL Current (No Load) ICC IEE ILL @ VIH, VIL = 5.0 V, 0 V @ VIH, VIL = 2.4 V, 0.4 V Power Supply Sensitivity with VOUT = 10 V Power Dissipation (Static, No Load) TEMPERATURE RANGE Specified Performance (A)
Min 16/18
Max
Units Bits
17
0.2 0.2 18 0.5 0.5
0.75 0.5 1 1 2 4
16-Bit LSB 16-Bit LSB Bits 16-Bit LSB 16-Bit LSB 16-Bit LSB 16-Bit LSB 16-Bit LSB/C 16-Bit LSB 16-Bit LSB 16-Bit LSB/C Bits mV ppm/C mV ppm/C % of FSR ppm/C % of FSR ppm/C k k V ppm/C mA pF mA ppm/1000 Hrs
0.015 2 4 0.015 14 2.5 3 10 5 0.10 25 0.05 10 7 7 9.99 2 10 10 10.00 4 1000 25 50 13 13 10.01 25
0 -10 5 25 0.9 2.0 0
+10 +10 1000 7 VLL 0.8 10 10
V V mA pF mA k V V A A V V
2.4 0.4
+14.25 -15.75 +4.75 +18 -18 2 3 600 -40
+15.75 -14.25 +5.25 +21
V V V mA mA mA mA ppm/% mW C
-21
3 7.5 1 725 +85
-2-
REV. A
AD760
NOTES 1 For 18-bit resolution, 1 LSB = 0.00038% of FSR. For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for full-scale range and is 10 V in unipolar mode and 20 V in bipolar mode. 2 Characteristics are guaranteed at V OUT Pin (23). 3 TCAL is the calibration temperature. 4 Gain Error is measured with a fixed 50 resistor as shown in Figure 5a and Figure 6a. 5 Gain Error and gain drift are measured with the internal reference. The internal reference is the main contributor to the gain drift. If lower drift is required, the AD760 can be used with a precision external reference such as the AD587, AD586 or AD688. 6 DAC Gain Error is measured without the on-chip voltage reference. It represents the performance that can be obtained with an external precision reference. 7 External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD760. 8 Operation on 12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference section. Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. (TMIN < TA < TMAX, VCC = +15 V, VEE = -15 V, VLL = +5 V, tested at VOUT except where noted.)
Parameter Output Settling Time (Time to +0.0008% FS, with 2 k , 1000 pF Load) Limit 13 8 10 6 8 2.5 Units s max s typ s typ s typ s typ s typ Test Conditions/Comments 20 V Step, TA = +25C 20 V Step, TA = +25C 20 V Step 10 V Step, TA = +25C 10 V Step 1 LSB Step Recovery time is referenced to the rising edge of CALOK, when MUXOUT switches from MUXIN to VOUT. MUXIN = VOUT prior to calibration. MUXIN, VOUT = -10 V to +10 V 0 dB, 1001 Hz. Sample Rate = 100 kHz. T A = +25C -20 dB, 1001 Hz. Sample Rate = 100 kHz. T A = +25C -60 dB, 1001 Hz. Sample Rate = 100 kHz. T A = +25C TA = +25C, byte load DAC alternately loaded with 8000H and 7FFFH 100 pF Load. MUXIN = VOUT = negative full scale DAC alternately loaded with 0000 H and FFFFH. CS high Measured at VOUT, 20 V span, excludes internal reference Measured at REF OUT
MUXOUT Recovery Time (Time to +0.0008% FS, with 100 pF Load) 2 Total Harmonic Distortion + Noise A, S Grade A, S Grade A, S Grade Signal-to-Noise Ratio Digital-to-Analog Glitch Impulse MUXOUT Glitch Impulse Digital Feedthrough Output Noise Voltage Density (1 kHz-1 MHz) Reference Noise (1 kHz-1 MHz)
Specifications are subject to change without notice.
s typ % max % max % max dB min nV-s typ nV-s typ nV-s typ nV/ Hz typ nV/ Hz typ
0.005 0.03 3.0 94 15 30 2 120 125
REV. A
-3-
AD760 TIMING CHARACTERISTICS (V
Parameter (Figure 1a) tCS tDS tDH tBES tBEH tLH tLW (Figure 1b) tCLK tLO tHI tDS tDH tLH tLW tPROP +25C 50 50 0 50 0 200 50 80 40 40 50 0 200 50 70 60 60 10 60 10 350 50 100 50 50 60 10 350 50 100
CC
= +15 V, VEE = -15 V, VLL = +5 V, VIH = 2.4 V, VIL = 0.4 V)
Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max Parameter (Figure 1c) tCLR tSET tHOLD (Figure 1d) tCAL tBUSY tCD tCS tCV +25C 100 100 0 50 200 170 150 150 Limit TMIN to TMAX 120 120 0 50 200 220 190 190 Units ns min ns min ns min ns min ms max ns max ns max ns max
Limit TMIN to TMAX
Specifications subject to change without notice.
DB0-7
tDS
HBE OR LBE
tDH
tBES tCS
CS
tBEH
tLH
LDAC
tLW
Figure 1a. AD760 Byte Load Timing
SIN
VALID 1
VALID 16/18
t DS t LO
CS
tDH tH I
tCLK
LDAC
tLH
tLW
tPROP
SOUT VALID 1
Figure 1b. AD760 Serial Load Timing
-4-
REV. A
AD760
tCLR
CLR
tSET
UNI/BIP CLR "1"= BIP, "0"= UNI
tHOLD
Figure 1c. Asynchronous Clear to Bipolar or Unipolar Zero
tCAL
CAL
tBUSY
CALOK
tCD tCS
HBE
tCV
Figure 1d. Calibration Timing
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION DIP
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +17.0 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -17.0 V VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V Digital Inputs (Pins 2, 7-14, and 16-21) to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 V to +7.0 V REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 V Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . . 10.5 V REF OUT, VOUT, MUXOUT, MUXIN . . . . . Indefinite Short to AGND, DGND, VCC, VEE, and VLL JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 50C/W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300C
*
CALOK CAL -VEE +VCC +VLL DGND DB7, 15 DB6, 14 DB5, 13
1 2 3 4 5 6 7 8 9
28 MUX 27 MUX
IN
OUT
26 REF OUT 25 REF IN 24 SPAN/BIP OFF
AD760
23 VOUT
22 AGND TOP VIEW (Not to Scale) 21 LDAC 20 19 CLR SER
DB4, 12 10 DB3, 11 11 DB2, 10, 18/16 SERIAL 12 DB1, 9, MSB/LSB 13 DB0, 8, SIN 14
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
18 HBE 17 LBE, UNI/BIP CLR 16 CS
15 SOUT
ORDERING GUIDE
Model AD760AQ
Temperature Range -40C to +85C
Package Description Cerdip
Package Option Q-28
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD760 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-5-
AD760
DEFINITIONS OF SPECIFICATIONS THEORY OF OPERATION
INTEGRAL NONLINEARITY: Analog Devices defines integral nonlinearity as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (a straight line drawn from 0 to FS - 1 LSB) for any bit combination. This is also referred to as relative accuracy. DIFFERENTIAL NONLINEARITY: Differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with a 1 LSB change in the digital input code. Monotonic behavior requires that the differential linearity error be greater than or equal to -1 LSB over the temperature range of interest. MONOTONICITY: A DAC is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function of the input. GAIN ERROR: Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. OFFSET ERROR: Offset error is a combination of the offset errors of the voltage-mode DAC and the output amplifier and is measured with all 0s loaded in the DAC. BIPOLAR ZERO ERROR: When the AD760 is connected for bipolar output and 10 . . . 000 is loaded in the DAC, the deviation of the analog output from the ideal midscale value of 0 V is called the bipolar zero error. DRIFT: Drift is the change in a parameter (such as gain, offset and bipolar zero) over a specified temperature range. The drift temperature coefficient, specified in ppm/C, is calculated by measuring the parameter at TMIN, 25C and TMAX and dividing the change in the parameter by the corresponding temperature change. TOTAL HARMONIC DISTORTION + NOISE: Total harmonic distortion + noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent (%). THD+N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and noise. The distribution of these errors may be different, depending upon the amplitude of the output signal. Therefore, to be the most useful, THD+N should be specified for both large and small signal amplitudes. SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is defined as the ratio of the amplitude of the output when a fullscale signal is present to the output with no signal present. This is measured in dB. DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is measured at half scale when the DAC switches around the MSB and as many as possible switches change state, i.e., from 011 . . . 111 to 100 . . . 000. DIGITAL FEEDTHROUGH: When the DAC is not selected (i.e., CS is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough.
The AD760 uses autocalibration circuitry to produce a true 16-bit DAC with typically 0.2 LSB Integral and Differential Linearity Error and 0.5 LSB Offset Error. The block diagram in Figure 2 shows the circuit components needed for calibration. The MAIN DAC uses an array of bipolar current sources with MOS current steering switches to develop a current proportional to the applied digital word, ranging from 0 mA to 2 mA. A segmented architecture is used, where the most significant four data bits are thermometer decoded to drive 15 equal current sources. The lesser bits are scaled using an R-2R ladder, then applied together with the segmented sources to the summing node of the output amplifier. An extra LSB is included in the MAIN DAC, for use during calibration. The self-calibration architecture of the AD760 attempts to reduce the linearity errors of its transfer function. The algorithm first checks for bipolar or unipolar operation, calibrates either bipolar zero or unipolar offset, and then removes the carry errors (DNL errors) associated with the upper 6 bits (64 codes). Once calibrated, the top six bits of a code entering the MAIN DAC simultaneously address the RAM, calling up a correction code that is then applied to the CALDAC. The output currents of both the MAIN DAC and CALDAC are combined in the summing amplifier to produce the corrected output voltage.
MSB/ 18/16 SIN LSB SERIAL OR OR OR DB0 DB1 DB2
14 13 12
CS UNI/ BIP CLR 17 OR LBE HBE 18 SER 19 CLR 20 LDAC 21 REF IN 25
16
DB7
7
AD760
CONTROL LOGIC
16/18-BIT INPUT REGISTER 10k 16/18-BIT DAC LATCH 10k MAIN DAC
15 SOUT
24
SPAN/ BIP OFF
9.95k RAM REF OUT 26 +10V REF
23 27 28
VOUT MUXOUT MUX IN AGND
CALIBRATION DAC
22
TRANSFER STD DAC
CALIBRATION SEQUENCER
1 2 3 4 5 6
CALOK
CAL
-VEE
+VCC
+VLL
DGND
Figure 2. Functional Block Diagram
In the first step of DNL calibration the output of the MAIN DAC is set to the code just below the code to be calibrated. The extra LSB in the MAIN DAC is turned on to find the extrapolated value for the next code. The comparator is then nulled using TRANSFER STD DAC. The voltage at VOUT has in effect been sampled at the code to be calibrated. Next, the extra LSB is turned off and the MAIN DAC code is incremented by one LSB. The comparator is once again nulled, this time with the CALDAC, until the VOUT is adjusted to equal the previously sampled output. The CALDAC code is stored in RAM and the process is repeated for the next code.
-6-
REV. A
AD760
CALIBRATED LINEARITY PERFORMANCE UNIPOLAR CONFIGURATION
The cumulative probability plots for the AD760 INL and DNL shown in Figures 3 and 4 represent the maximum absolutevalue (peak) linearity error for each part. Roughly 100 parts from each of 3 wafer lots were used. The calibrated DNL and INL performance for the sample populations shown also represent the expected performance for a single part calibrated often. There is essentially no difference between the expected performance of many parts calibrated once and one part calibrated often. The AD760 calibrated performance is guaranteed at any temperature within the operating temperature range. The peak nonlinearity for the sample populations shown are also representative of the expected maximum linearity errors of a single part recalibrated at temperature.
100 40 80 30 60
COUNT CUMULATIVE PROBABILITY - %
The configuration shown in Figure 5a will provide a unipolar 0 V to +10 V output range. In this mode a 50 resistor is tied between REF OUT (Pin 26) and REF IN (Pin 25). It is possible to use the AD760 without any external components by tying Pin 26 directly to Pin 25. Eliminating this resistor will increase the gain error by 0.50% of FSR.
AD760
25 REFIN
50 +10V REF 9.95k 10k 24 10k MAIN DAC 23 VOUT 26 REFOUT SPAN/BIP OFF
Figure 5a. 0 V to +10 V Unipolar Voltage Output
20 40
10
If it is desired to adjust the gain error to zero, this can be accomplished using the circuit shown in Figure 5b. The adjustment procedure is as follows: STEP 1 . . . OFFSET ADJUST Initiate calibration sequence. CALOK (Pin 1) must remain high throughout Gain Adjust. STEP 2 . . . GAIN ADJUST Turn all bits ON and adjust gain trimmer, R1, until the output is 9.999847 volts. (Full scale is adjusted to 1 LSB less than the nominal full scale of 10.000000 volts.)
AD760
REFIN R1 100 REFOUT SPAN/BIP OFF
20
0 0 0.125 0.25 0.375 16-BIT LSB 0.5 0.625
0 0.75
Figure 3. AD760 Peak INL
50 100
40
80
30
COUNT
60
CUMULATIVE PROBABILITY - %
25
+10V REF 9.95k 10k
26 24
20
40
10k MAIN DAC 23 VOUT
10
20
0 0 0.125 0.25 16-BIT LSB 0.375 0.5
0
Figure 4. AD760 Peak DNL
ANALOG CIRCUIT CONNECTIONS
Figure 5b. 0 V to +10 V Unipolar Voltage Output with Gain Adjust
BIPOLAR CONFIGURATION
Internal scaling resistors provided in the AD760 may be connected to produce a unipolar output range of 0 V to +10 V or a bipolar output range of -10 V to +10 V. Gain and offset drift are minimized in the AD760 because of the thermal tracking of the scaling resistors with other device components.
The circuit shown in Figure 6a will provide a bipolar output voltage from -10.000000 V to +9.999694 V with positive full scale occurring with all bits ON. As in the unipolar mode, resistor R1 may be eliminated altogether to provide AD760 bipolar operation without any external components. Eliminating this resistor will increase the gain error by 0.50% of FSR in the bipolar mode.
REV. A
-7-
AD760
AD760
25 REFIN R1 50 REFOUT
INTERNAL/EXTERNAL REFERENCE USE
+10V REF 9.95k 10k
26 24
10k MAIN DAC
SPAN/ BIP OFF
The AD760 has an internal low noise buried Zener diode reference that is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for use in a high speed DAC and will give long-term stability equal or superior to the best discrete Zener diode references. The performance of the AD760 is specified with the internal reference driving the DAC and with the DAC alone (for use with a precision external reference). The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 1 mA to REF IN and 1 mA to BIPOLAR OFFSET). A minimum of 2 mA is available for driving external loads. The AD760 reference output should be buffered with an external op amp if it is required to supply more than 4 mA total current. The reference is tested and guaranteed to 0.1% max error. It is also possible to use external references other than 10 volts with slightly degraded linearity specifications. The recommended range of reference voltages is +5 V to +10.24 V. For example, by using the AD586 5 V reference, outputs of 0 V to +5 V or 5 V can be realized. Using the AD586 voltage reference makes it possible to operate the AD760 with 12 V supplies with 10% tolerances. Figure 7 shows the AD760 using the AD586 precision 5 V reference in the bipolar configuration. The highest grade AD586MN is specified with a drift of 2 ppm/C. This circuit includes an optional potentiometer that can be used to adjust the gain error in a manner similar to that described in the Bipolar Configuration section. Use +4.999847 V as the full-scale output value. The AD760 can also be used with the AD587, 10 V reference, using the same configuration shown in Figure 7 to produce a 10 V output. The highest grade AD587L is specified at 5 ppm/C.
AD760
25 REFIN +VCC 100 2
23 VOUT
Figure 6a. 0 V to 10 V Bipolar Voltage Output
Gain Error can be adjusted to zero using the circuit shown in Figure 6b. Note that gain adjustment changes the Bipolar Zero by one half of the variation made to the full-scale output value. Therefore, to eliminate iterating between Zero (calibration) and Gain adjustment the following procedure is recommended. STEP 1 . . . ZERO ADJUST Initiate Calibration Sequence. STEP 2 . . . GAIN ADJUST Insure the CALOK pin remains high throughout the gain adjustment process. Turn all bits on and measure the output error relative to the full-scale output of 9.99695 V. Adjust R1 until the output is minus two times the full-scale output error. For example, if the output error is -1 mV, adjust the output 2 mV higher than the previous full-scale error. STEP 3 . . . ZERO ADJUST Initiate Calibration Sequence. The AD760 will calibrate Bipolar Zero and the resulting Gain Error will be very small. Reload the DAC with all ones to check the full-scale output error.
AD760
25 REFIN R1 100 REFOUT
+10V REF 9.95k 10k
26 24
AD586
+10V REF
SPAN/ BIP OFF
26 REFOUT VOUT 24 SPAN/BIP OFF
6
10k MAIN DAC
9.95k
10k 10k
4
23 VOUT
MAIN DAC 23 VOUT
Figure 6b. 0 V to 10 V Bipolar Voltage Output Gain Adjustment
It should be noted that using external resistors will introduce a small temperature drift component beyond that inherent in the AD760. The internal resistors are trimmed to ratio-match and temperature-track other resistors on chip, even though their absolute tolerances are 20% and absolute temperature coefficients are approximately -50 ppm/C. In the case that external resistors are used, the temperature coefficient mismatch between internal and external resistors, multiplied by the sensitivity of the circuit to variations in the external resistor value, will be the resultant additional temperature drift.
Figure 7. Using the AD760 with the AD586 5 V Reference
OUTPUT SETTLING AND GLITCH
The AD760's output buffer amplifier typically settles to within 0.0008% FS (1/2 LSB) of its final value in 8 s for a full-scale step. Figures 8a and 8b show settling for a full scale and an LSB step, respectively, with a 2 k , 1000 pF load applied. The guaranteed maximum settling time at +25C for a full-scale step is 13 s with this load. The typical settling time for a 1 LSB step is 2.5 s.
-8-
REV. A
AD760
The digital-to-analog glitch impulse is specified as 15 nV-s typical. Figure 8c shows the typical glitch impulse characteristic at the code 011 . . . 111 to 100 . . . 000 transition when loading the second rank register from the first rank register. A Power-On-Reset feature senses whenever any power supply is low enough to jeopardize the integrity of the calibration data in the RAM. At power-up or in the event of a power supply transient, CALOK (Pin 1) is low and the MUXOUT pin is switched to MUXIN. Self-Calibration is initiated by strobing the CAL pin low (refer to Figure 1d). The CALOK pin will go low and the MUXOUT pin is connected to MUXIN. During calibration, the second-rank latch is transparent to allow the CALIBRATION SEQUENCER to control the MAIN DAC. After successful completion of calibration, the input to the second-rank latch is switched to the first-rank latch, the DAC is loaded with the contents of the firstrank latch, VOUT settles to the value represented by the data in the first-rank latch, then CALOK will go high, and MUXOUT is switched to VOUT. Therefore the user should program the DAC with the desired data before initiating the calibration. The second rank latch, controlled by LDAC, is a transparent latch. As long as LDAC remains high, changes in the first rank latch will be reflected in the DAC output immediately. The status of the calibration may be determined by taking the HBE pin low. CALOK either switches high if the calibration is in progress, or CALOK remains low if a power supply voltage transient has interrupted the calibration and caused the AD760 to be set to the uncalibrated state. When CLR is strobed, Pin 17 functions as a control input, UNI/ BIP CLR, that determines how the Asynchronous Clear function works (refer to Figure 1c). If the UNI/BIP CLR pin is a logic low when CLR is strobed the DAC is set to minus fullscale; a logic high sets the DAC to midscale. It should be noted that the clear function clears the DAC Latch but does not clear the first rank latch. Therefore, the data that remains in the first rank latch can be reloaded by simply bringing LDAC high again. Alternately, new data can be loaded into the first rank latch if desired. Serial Mode Operation is enabled by bringing the SER (Pin 19) low. This changes the function of DB0 (Pin 14) to that of the serial input pin, SIN. The function of DB1 (Pin 13) also changes to a control input, MSB/LSB that determines which bit is to be loaded first. Sixteen or Eighteen-Bit Operation is selected with another dual use pin. DB2 (Pin 12) changes to a control input, 18/16SERIAL, that selects whether 16-bit or 18-bit serial data is to be used. For 16-bit operation the data inputs, Pins 7-12, should be tied low. For 18-bit operation Pin 12 must be tied high. Data is clocked into the input shift register on the rising edge of CS as shown in Figure 1b. The data is then resident in the first rank latch and can be loaded into the DAC by taking the LDAC pin high. This will cause the DAC to change to the appropriate output value. In serial mode the byte controls HBE (Pin 18) and LBE (Pin 17) are disabled. Pin 17 can be tied to a logic high or low depending on how the user wants the asynchronous clear function to work. The Serial Out pin (SOUT) can be used to daisy chain several DACs together in multi-DAC applications to minimize the number of control lines required. The first rank latch simply acts as a shift register, and repeated strobing of CS will shift the data out through SOUT and into the next DAC. Each DAC in the chain will require its own LDAC signal unless all of the DACs are to be updated simultaneously.
600 +10 400 200 0 0 -200 -10 -400 -600 10 s 20
VOLTS
0
a. -10 V to +10 V Full-Scale Step Settling
600 400 200
V
0
-200 -400 -600 0 2 3 4 5
1
s
b. LSB Step Settling
+20
mV
0
-20
0
1
2
s
3
4
5
c. D-to-A Glitch Impulse Figure 8. Output Characteristics
DIGITAL CIRCUIT DETAILS
The AD760 has several "dual-use" pins that allow flexible operation while maintaining the lowest possible pin count and consequently the smallest package size. The following information is useful when applying the AD760. The AD760 uses an internal Output Multiplexer to disconnect the DAC output from MUXOUT (Pin 27) when the device is uncalibrated or when a calibration sequence is in progress. At those times MUXOUT is switched to MUXIN (Pin 28) so the user can force a predetermined output voltage. Refer to the following section for using the output multiplexer. REV. A -9-
V
AD760
Byte Mode Operation is enabled by setting SER high, which configures DB0-DB7 as data inputs. In this mode HBE and LBE are used to identify the data as either the high byte or the low byte of the 16-bit word. The user can load the data in either order into the first rank latch using the rising edge of the CS signal as shown in Figure 1a. The status of Pin 17 when CLR is strobed determines whether the AD760 clears to unipolar or bipolar zero. (But it cannot be hardwired to the desired state, as in the serial mode.) NOTE: CS is edge triggered. HBE, LBE, CLR, SER, CAL, and LDAC are level triggered.
USING THE OUTPUT MULTIPLEXER
3 -VEE +VCC 4 1 CALOK +VCC
AD760
24
SPAN/ BIP OFF 2 7
0.1F
23
VOUT MUX O UT 3
AD707
OR
OUTPUT 6 1k
AD820 4 0.1F 100pF
27 28 22 MUXI N AGND
-VEE
The onboard multiplexer allows the user to isolate the load from the voltage variations at VOUT during calibration. To minimize the glitch-impulse at MUXOUT, the multiplexer input, MUXIN, should be tied to a voltage equal to the DAC's negative full-scale voltage. Since the DAC is loaded with the contents of its first-rank latch before completing calibration, the DAC should be programmed to negative full scale before calibrating. This will minimize the voltage excursions of MUXOUT at the beginning and end of calibration. If the glitch-impulse at the beginning of calibration is not important, yet the user wants to minimize the recovery time at MUXOUT, MUXIN should be set to the voltage that corresponds to the data in the first-rank latch before calibration is initiated. The multiplexer series on-resistance limits its load-drive capability. To attain 16-bit linearity, MUXOUT must be buffered with a suitable op amp. The amplifier open loop-gain and commonmode rejection contribute to gain error whereas the linearity of these parameters affect the relative accuracy (or integral nonlinearity). In general, the amplifier linearity is not specified so its effects must be determined empirically. Using the AD707, as shown in Figure 9, the overall linearity error is within 0.5 LSB. The AD707C/T initial voltage offset and its temperature coefficient will not contribute more than 0.1 LSB to the Bipolar Zero Error over the entire operating temperature range. The settling time to 1/2 LSB is typically 100 s for a 20 V step. For applications that require faster settling, the AD820 can be used to attain full-scale settling to within a 1/2 LSB in 20 s. The additional linearity error from the AD820 will be no more than 0.25 LSB.
+VCC 4 1 CALOK
Figure 9. Buffering the AD760 Internal MUX
USING AN EXTERNAL MULTIPLEXER
An external multiplexer like the ADG419 allows the user to minimize the glitch impulse when holding the output to any predetermined voltage during calibration. The ADG419 can be used with a high speed op amp like the AD829, as shown in Figure 10, to attain the fastest possible settling time while maintaining 16-bit linearity. The settling time to 1/2 LSB for a 20 V step is typically 10 s.
AD760 TO MC68HC11 (SPI* BUS) INTERFACE
The AD760 interface to the Motorola SPI (serial peripheral interface) is shown in Figure 11. The MOSI, SCK, and SS pins of the HC11 are respectively connected to the SIN, CS and LDAC pins of the AD760. The majority of the interfacing issues are taken care of in the software initialization. A typical routine such as the one shown below begins by initializing the state of the various SPI data and control registers. The most significant data byte (MSBY) is then retrieved from memory and processed by the SENDAT subroutine. The SS pin is driven low by indexing into the PORTD data register and clearing Bit 5. The MSBY is then sent to the SPI data register where it is automatically transferred to the AD760.
*SPI is a registered trademark of Motorola.
+VCC 4
ADG419 AD760
24 SPAN/ BIP OFF 6
+VCC 0.1F
23
VOUT
8
2
7
AD829
5 1 1nF 2 7 -VEE -VEE 0.1F 3 4
6 1k 60pF
OUT
27 MUXOUT 28 22 3 -VEE MUXIN AGND
Figure 10. Using the AD760 with an External MUX
-10-
REV. A
AD760
The HC11 generates the requisite 8 clock pulses with data valid on the rising edges. After the most significant byte is transmitted, the least significant byte (LSBY) is loaded from memory and transmitted in a similar fashion. To complete the transfer, the LDAC pin is driven high latching the complete 16-bit word into the AD760. INIT
LDAA STAA LDAA STAA LDAA STAA #$2F PORTD #$38 DDRD #$50 SPCR ;SS = 1; SCK = 0; MOSI = I ;SEND TO SPI OUTPUTS ;SS, SCK,MOSI = OUTPUTS ;SEND DATA DIRECTION INFO ;DABL INTRPTS,SPI IS MASTER & ON ;CPOL=0, CPHA=0,1MHZ BAUD RATE
the frequency range of interest. The AD760's noise spectral density is shown in Figures 13 and 14. Figure 13 shows the DAC output noise voltage spectral density for a 20 V span excluding the reference. This figure shows the l/f corner frequency at 100 Hz and the wideband noise to be below 120 nV/ Hz. Figure 14 shows the reference wideband noise to be below 125 nV/ Hz.
1000 Hz NOISE VOLTAGE - nV/ 100 10 1 1
NEXTPT LDAA BSR JMP SENDAT LDY BCLR STAA WAIT1 LDAA BPL LDAA STAA LDAA BPL BSET RTS
MSBY ;LOAD ACCUM W/UPPER 8 BITS SENDAT ;JUMP TO DAC OUTPUT ROUTINE NEXTPT ;INFINITE LOOP #$1000 ;POINT AT ON-CHIP REGISTERS $08,Y,$20 ;DRIVE SS (LDAC) LOW SPDR ;SEND MS-BYTE TO SPI DATA REG SPSR WAIT1 LSBY SPDR ;CHECK STATUE OF SPIE ;POLL FOR END OF X-MISSION ;GET LOW 8 BITS FROM MEMORY ;SEND LS-BYTE TO SPI DATA REG
10
100
100k 1k 10k FREQUENCY - Hz
1M
10M
Figure 13. DAC Output Noise Voltage Spectral Density
1000
Hz NOISE VOLTAGE - nV/
WAIT2
SPSR ;CHECK STATUS OF SPIE WAIT2 ;POLL FOR END OF X-MISSION $08,Y,$20 ;DRIV SS HIGH TO LATCH DATA
68HC11
MOSI SCK SS
100
SIN CS LDAC SER
AD760
10
Figure 11. AD760 to 68HC11 (SPI) Interface
1 1 10 100 1k 10k 100k 1M 10M
AD760 TO MICROWIRE INTERFACE
FREQUENCY - Hz
The flexible serial interface of the AD760 is also compatible with the National Semiconductor MICROWIRE* interface. The MICROWIRE* interface is used on microcontrollers such as the COP400 and COP800 series of processors. A generic interface to the MICROWIRE interface is shown in Figure 12. The G1, SK, and SO pins of the MICROWIRE interface are respectively connected to the LDAC, CS and SIN pins of the AD760.
MICROWIRE SO SK G1 SIN CS LDAC SER
Figure 14. Reference Noise Voltage Spectral Density
BOARD LAYOUT
AD760
Designing with high resolution data converters requires careful attention to board layout. Trace impedance is the first issue. A 306 A current through a 0.5 trace will develop a voltage drop of 153 V, which is 1 LSB at the 16-bit level for a 10 V full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to filter out ac noise. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog and digital ground planes should also be used, with a single interconnection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them at right angles.
Figure 12. AD760 to MICROWIRE Interface
NOISE
In high resolution systems, noise is often the limiting factor. A 16-bit DAC with a 10 volt span has an LSB size of 153 V (-96 dB). Therefore, the noise must remain below this level in
*MICROWIRE is a registered trademark of National Semiconductor.
REV. A
-11-
AD760
One feature that the AD760 incorporates to help the user layout is that the analog pins (VCC, VEE, REF OUT, REF IN, SPAN/ BIP OFFSET, VOUT, MUXOUT, MUXIN and AGND) are adjacent to help isolate analog signals from digital signals.
SUPPLY DECOUPLING GROUNDING
Decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. A 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor provides adequate decoupling. VCC and VEE should be bypassed to analog ground, while VLL should be decoupled to digital ground. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD760, associated analog circuitry and interconnections as far as possible from logic circuitry. A solid analog ground plane around the AD760 will isolate large switching ground currents. For these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit construction is preferred.
If a single AD760 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD760. If multiple AD760s are used or the AD760 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from flowing through the analog ground.
PACKAGE INFORMATION 28-Pin Cerdip Package (Q-28)
1.490 (37.84) MAX 28 15 0.525 (13.33) 0.515 (13.08) 1 14 0.125 (3.175) MIN 0.18 (4.57) MAX
GLASS SEALANT
0.620 (15.74) 0.590 (14.93)
0.22 (5.59) MAX 0.02 (0.5) 0.016 (0.406)
0.012 (0.305) 0.008 (0.203) 0.11 (2.79) 0.099 (2.28) 0.06 (1.52) 0.05 (1.27) 15 0
-12-
REV. A
PRINTED IN U.S.A.
C2023-18-4/95
The AD760 power supplies should be well filtered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate spikes which can induce noise in the analog system.
The AD760 has two pins, designated analog ground (AGND) and digital ground (DGND.) The analog ground pin is the "high quality" ground reference point for the device. Any external loads on the output of the AD760 should be returned to analog ground. If an external reference is used, this should also be returned to the analog ground.

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